The present invention relates to a semiconductor integrated circuit provided with a self-diagnosis test circuit function and the test method of the semiconductor integrated circuit, particularly relates to an effective test circuit for a burn-in test and its test method.
In a burn-in test which is one of a reliability test of a semiconductor integrated circuit, an internal circuit is operated in a state close to actual operation and stress is applied, however, as a conventional burn-in test was made for a packaged finished product, a method of inputting a required input signal to a pin from an external signal supply unit and operating an internal circuit was taken.
However, recently, the technique of wafer level burn-in by which a great many semiconductor integrated circuits can be simultaneously tested is also being established and the need for the test of a semiconductor integrated circuit having a great many pins increases. In the case of a test depending upon external connection, the number of pins which can be used for input is limited, compared with a burn-in test of a conventional type packaged product and therefore, a method of applying stress to a circuit by providing a pseudo-random number generating circuit inside and making scan using the output signal as an input signal including a scan chain is proposed.
However, according to the method, appropriate stress cannot be applied to an I/O cell except a pin used for input of an external signal supply unit and a pin from which an output signal of the final section of a scan chain is output.
There is a method of providing an output determination circuit to a circuit provided with a scan function and checking whether appropriate stress is applied in a burn-in test or not. However, in a method of operating CPU according to an instruction written in test ROM and applying stress to an asynchronous circuit and a memory cell respectively without a scan function, a case that appropriate stress is not applied because of a malfunction of test ROM and others cannot be discriminated from a case that appropriate stress is applied.
The invention is made in view of the actual situation and provides a test circuit for a semiconductor integrated circuit and its test method wherein appropriate stress can be applied to all I/O cells only by adding a slight circuit in a test.
The invention also provides a test circuit for a semiconductor integrated circuit and its test method wherein it can be further checked whether appropriate stress is applied to an asynchronous circuit and a memory cell respectively without a scan function or not.
A semiconductor integrated circuit provided with a first self-diagnosis test circuit function according to the invention is based upon a semiconductor integrated circuit provided with CPU and is characterized in that it is provided with a port signal output setting register that outputs a high level and a low level to an I/O cell in a test according to test ROM in which instructions for operating CPU in a test mode are written.
According to the circuit configuration, in case an internal circuit is made to scan to apply stress in a test such as a burn-in test, appropriate stress can be also applied to an I/O cell except a pin used for input from an external signal supply unit and a pin to which an output signal of the final section of a scan chain is output.
A second aspect of the invention is based upon the semiconductor integrated circuit provided with a self-diagnosis test circuit function according to the first aspect of the invention and is characterized in that a semiconductor integrated circuit is provided with a port signal output setting register that outputs a high level and a low level to all I/O cells.
According to such configuration, a self-diagnosis test can be easily made to all I/O cells.
A third aspect of the invention is based upon the semiconductor integrated circuit provided with a self-diagnosis test circuit function according to the first aspect of the invention and is characterized in that in a semiconductor integrated circuit, ROM in which instructions for operating CPU are written is also connected to an I/O cell provided with a port signal output setting register in a test mode and a port signal output setting register that outputs a high level and a low level only for a test is provided to an I/O cell not provided with the port signal output setting register.
According to such configuration, all I/O cells are provided with the port signal output setting register and a self-diagnosis test can be easily made to all the I/O cells.
A fourth aspect of the invention is based upon a semiconductor integrated circuit provided with the self-diagnosis test circuit function according to the first aspect of the invention and is characterized in that a test is a burn-in test.
As in the burn-in test, heat treatment for a long time was performed under high temperature, it was extremely difficult to execute a probe test for all pins under high temperature and it was heretofore extremely difficult to execute the test for all I/O cells, however, according to such configuration, a burn-in test can be easily executed.
A fifth aspect of the invention is based upon a semiconductor integrated circuit provided with CPU and is characterized in that a test process in which appropriate stress is applied to all I/O cells by sending an instruction for operating CPU in a test mode and inputting/outputting a test signal including a high level and a low level to/from all the I/O cells is included.
Though it is impossible to test all I/O cells by a conventional type method, according to such configuration according to the invention, a self-diagnosis test can be executed for all I/O cells. Therefore, in any environment such as in a burn-in test, a test can be extremely easily executed.
A sixth aspect of the invention is based upon the test method of the semiconductor integrated circuit according to the fifth aspect of the invention and is characterized in that the test method includes a test process in which appropriate stress is applied to an I/O cell by sending an instruction for operating CPU via test ROM in a test mode in a semiconductor integrated circuit provided with CPU and inputting/outputting a high level and a low level from/to aport signal output setting register to/from the I/O cell.
According to such configuration, a test can be extremely easily executed.
A seventh aspect of the invention is based upon the semiconductor integrated circuit provided with the self-diagnosis test circuit function according to the first aspect of the invention and is characterized in that a semiconductor integrated circuit provided with CPU is provided with test ROM in which instructions for operating CPU in a test mode are written and a circuit for determining whether test ROM is correctly operated to the end in a test or not by writing an instruction for setting a flag in a test ROM determination register in a final part of the test ROM and outputting the flag to an external terminal.
According to such configuration, in the case of a burn-in test, as it can be judged whether stress is actually applied or not after a test process for a long time is finished, the result of the test can be verified. Also, according to this circuit configuration, it can be checked whether stress is correctly applied or not even if CPU is operated and stress is applied to an asynchronous circuit and a memory cell respectively without a scan function according to an instruction written to test ROM.
An eighth aspect of the invention is based upon the semiconductor integrated circuit provided with the self-diagnosis test circuit function according to the seventh aspect of the invention and is characterized in that even if a flag of the test ROM determination register is fixed because of any cause in a test, the register composed of plural bits is provided so that it can be determined whether test ROM is correctly operated to the end or not.
According to this circuit configuration, even if a flag of the test ROM determination register is fixed because of any cause in a test such as a burn-in test, it can be determined whether test ROM is correctly operated to the end or not.